1. Field of the Invention
The present invention relates to a display device and a method of fabricating a display device, and more particularly, to a liquid crystal display device and a method of fabricating a liquid crystal display device.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device controls light transmittance of a liquid crystal material using an electric field to display images.
FIG. 1 is a schematic plan view of an LCD device according to the related art. In FIG. 1, an LCD device includes an LCD panel 5 having liquid crystal cells arranged in a matrix configuration, and a driving circuit 7 for driving the LCD panel 5.
Although not shown, gate lines and data lines are arranged to cross each other within the LCD panel 5. Each of the liquid crystal cells is positioned at each area where the gate lines cross the data lines. In addition, the LCD panel 5 is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor (TFT), which functions as a switching device, to any one of the data lines. Similarly, the gate electrodes of the TFT are connected to any one of the gate lines, thereby allowing a pixel voltage signal to be supplied to the pixel electrodes for each of the data lines.
The TFT allows the pixel voltage signal to be charged in a corresponding pixel electrode in response to a gate high voltage Vgh transmitted along the gate lines. Accordingly, the liquid crystal cells charge the corresponding pixel voltage signals from the data lines when the TFT is turned ON due to the gate high voltage Vgh that is sequentially supplied along the gate lines, and any remaining charge is retained when the TFT is turned ON again. The pixel voltage signal is to be charged in the liquid crystal cell of a certain nth-numbered gate line remaining due to a storage capacitor Cst (not shown) formed by an overlap of the pixel electrode and the gate line of a previous stage gate line.
In general, the gate high voltage Vgh is supplied to each of the gate lines for every frame only during a period of time that the gate line is driven, i.e., only during one horizontal period 1H allowing the pixel voltage signal charged in the pixel electrode, and a gate low voltage Vg1 is supplied during a rest period. The storage capacitor Cst remains charged with a voltage charged to the pixel electrode of a present stage gate line by the gate low voltage Vg1 supplied to the gate line of the previous stage gate line.
In FIG. 1, the driving circuit 17 includes a gate driver 27 for driving the gate lines, a data driver 17 for driving the data lines, a timing controller ˜11 for controlling the gate driver 27 and the data driver 17, and a power supply (not shown) for supplying various driving voltages used in the LCD panel 5. The timing controller 11 controls driving timing of the gate driver 27 and the data driver 17, and supplies a pixel data signal to the data driver 17. The power supply generates driving voltages, such as the gate high voltage Vgh and the gate low voltage Vg1. The gate driver 27 sequentially supplies scanning signals to the gate lines to sequentially drive the liquid crystal cells on the LCD panel 5 on a one gate line-by-one gate line basis. The data driver 17 supplies data voltage signals to each of the data lines whenever the gate signal is supplied to any one of the gate lines. Accordingly, the LCD controls light transmittance by an electric field supplied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, and thereby displays images.
The data driver 17 and the gate driver 27 are directly connected to the LCD panel 5, and are both integrated into a plurality of integrated circuits (IC's). In addition, each of the data drive ICs 15 and the gate drive ICs 25 are mounted in a tape carrier package (TCP) to be connected to the LCD panel 5 using a tape automated bonding (TAB) system, or mounted onto the LCD panel 5 by a chip on glass (COG) system.
In FIG. 1, the drive IC's 15 and 25 are connected, via the TCPs 13 and 23, to the LCD panel 5 by the TAB system, and are connected to each other and receive control signals and direct current voltage signals input from an exterior over signal lines mounted onto a printed circuit board (PCB) 31 and 33 connected to the TCPs 13 and 23. For example, the data drive IC's 25 are connected in series via signal lines mounted on a data PCB, and commonly receive control signals and pixel data signals from the timing controller 11 and driving voltages from the power supply. The gate drive IC's 25 are connected in series via signal lines mounted on the gate PCB 33, and commonly receive control signals from the timing controller and driving voltages from the power supply.
FIG. 2 is a schematic plan view of an LCD device having a gate driving circuit according to the related art. In FIG. 2, a gate driving circuit is mounted onto an LCD panel for manufacturing a thinner type LCD device, thereby reducing manufacturing costs.
FIG. 3 is a schematic plan view of an LCD device having a gate driving circuit and a data driving circuit according to the related art. In FIG. 3, an LCD panel includes a gate driving circuit, as well as a portion of a data driving circuit, formed on the LCD panel.
Switching devices have been proposed in the U.S. Pat. No. 6,522,768, which is hereby incorporated by reference in its entirety, that may be used in a driving circuit of an LCD device. Accordingly, although the switching devices, i.e., TFTs, have rapid response speeds, the TFTs are formed of amorphous silicon fabricated using simple processes and have relatively good uniformity rather than formed of polycrystalline silicon fabricated using more difficult processes, such as crystallizing a silicon layer using a laser beam.
FIG. 4 is a schematic plan view of a switching device for a driving circuit according to the related art. In FIG. 4, a switching device may be composed of a TFT that includes a gate electrode 56 connected to a gate line 52 formed on a lower substrate, a source electrode 60 connected to a source line 64, a drain electrode 72 connected to a drain line 73 arranging in opposition to the source electrode 60, and a semiconductor layer 68 forming a channel between the source electrode 60 and the drain electrode 72, and an insulating film (not shown). In addition, the semiconductor layer 68 has a stacked active layer configuration including the source electrode 60, the drain electrode 72, and an ohmic contact layer for providing ohmic contact between the source and drain electrodes 60 and 72 and the semiconductor layer 68.
In FIG. 4, the switching device has a relatively wide channel width W1 for switching relatively high voltages. For example, the switching device has the relatively wide channel width W1 contrary to a configuration in which a TFT is provided within a pixel region and configured to include a plurality of TFTs provided within a pixel region, which has been proposed in the Japanese Laid-Open Patent No. H5-341316. For instance, the channel width W1 of the TFT formed within the pixel region is within a range of several to several tens of micrometers, and the channel width of the driving circuit is within a range of several thousand to several tens of thousand of micrometers.
FIG. 5 is a graph demonstrating a relation between channel width and current variation according to the related art, and FIG. 6 is a graph demonstrating a relation between channel width and electric charge mobility according to the related art. In FIGS. 5 and 6, a current variation flowing within a channel of a switching device decreases, and an electric charge mobility also decreases depending on an increase of a channel width of the switching device.
For example, although the switching device has a relatively wide channel width for switching relatively high voltages, the decrease of the variation of the current flowing within the channel of the switching device is dependent upon the increase of the channel width of the switching device. Moreover, a current efficiency is decreased depending on the increase of the channel width, as shown in FIG. 5. Furthermore, since the current efficiency decreases depending on the increase of the channel width, the electric charge mobility decreases, thereby reducing response speed of the switching device.
In addition, when the switching device becomes damaged due to sparks created during fabricaton processes or as a result of overcurrents, switching characteristic of the switching device deteriorates, thereby providing abnormal driving characteristics.